SourceCircuit Representation Learning with Masked Gate Modeling and Verilog-AIG Alignment
The paper evaluates DeepGate2's ability to predict the quality of logic synthesis optimization sequences. Using circuit embeddings extracted from AIGs, DeepGate2 ranks 1500 optimization sequences per design. Across 10 evaluation designs (bc0, apex1, div, k2, i10, mainpla, or1200 cpu, picorv32, rocket, sqrt), DeepGate2 achieves an average NDCG@3 of 0.334, NDCG@5 of 0.324, top-3% commonality of 0.116, top-5% of 0.157, and top-10% of 0.226.